Jiayu Lab

JiaYu Zhao

Electronic Information Engineering | FPGA, Embedded Systems and Communications

I work across principles, algorithms, RTL or firmware, simulation, compilation, testing, debugging and documented handoff. I value inspectable results and explicitly separate verified software boundaries from hardware work that still requires physical confirmation.

jiayuhere@gmail.com GitHub @jiayu-here WeChat jiayu_here www.jiayuhere.com
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Profile

Electronic information engineering graduate building long-term practice across communication theory, DSP, FPGA RTL, STM32/FreeRTOS and Python tooling. Projects retain source, testbenches, constraints, build evidence, firmware, scripts, documentation and known limitations wherever possible.

  • Break communication and control problems into independently verifiable algorithms, timing, interfaces and presentation layers.
  • Use waveforms, logs, serial data, test scripts and build reports to locate defects and retain evidence.
  • Distinguish simulation, compilation, timing closure and physical verification rather than presenting plans as completed results.

Selected Projects

FPGA QPSK Baseband Link and Visualization System

Verilog | UART | Python

Implemented PRBS7, Gray mapping, a discrete phase channel, hard decisions, BER counting and UART telemetry on Cyclone IV E, with Python constellation, I/Q and error visualization.

  • Resolved transmit-reference pipeline alignment, signed-width handling and UART throughput limits.
  • ModelSim and CSV flows pass; Quartus compilation and timing checks produce a `.sof` image.
Compilation and simulation complete | Physical UART confirmation pending

Multi-Function FPGA DDS Signal and Measurement System

DDS | I2C | AD/DA

Built sine, square, sawtooth and triangle DDS with PCF8591T ADC/DAC access, sample statistics and a 74HC595 six-digit display.

  • Implemented a 32-bit phase accumulator, 256-entry LUT, I2C state machine and exponential averaging.
  • ModelSim passes; Quartus completes synthesis, fitting, assembly and TimeQuest checks.
Compilation and simulation complete | Analog board measurement pending

STM32F103 FreeRTOS Multi-Mode Smart Car

C | FreeRTOS | PID

Designed dual-wheel PID, encoder odometry, line following, avoidance, Flash parameters, safety protection and Bluetooth commands for C8T6/RCT6 targets.

  • Separated safety, control, communications, behavior, sensing, display and monitoring tasks around a 10 ms control loop.
  • Both MCU targets cross-build and PID/protocol host tests pass, producing ELF, HEX, BIN, MAP and checksums.
Software build complete | Vehicle electrical, mechanical and calibration tests pending

Mathematical Modeling: Accurate Localization of Multiple Rocket Debris Objects

Mathematical Modeling | Localization Analysis | Second Prize

Modeled and analyzed the accurate localization of multiple rocket debris objects, translating the real-world positioning problem into solvable constraints and a complete competition submission.

Competition Project | Second Prize in Mathematical Modeling

STM32F103 Dual-Channel Temperature Monitoring and Alarm System

STM32 | DS18B20 | PT100 | OLED | FatFs

Samples a DS18B20 digital sensor and PT100 module voltage on STM32F103C8T6, with OLED display, threshold alarms, SD-card CSV logging, serial configuration and persistent Flash thresholds.

  • Uses non-blocking periodic scheduling for acquisition, alarms, display, storage and serial tasks, confirming two consecutive out-of-range readings before alarming.
  • The repository includes STM32 HAL, Keil/CubeMX projects, FatFs, documentation and a flashable HEX; the reserved ESP-01S cloud flow is disabled by default.
Independent Development | 2024.05 - 2024.06 | Public repository packaged 2026.07 Open GitHub Repository

STM32 Vision-Guided Robotic Arm Sorter

STM32 | FreeRTOS | OpenCV | Inverse Kinematics

Built a vision-guided sorting loop around STM32F103C8T6, Python and OpenCV, covering color detection, four-point hand-eye calibration, task queuing, a CRC16 serial protocol, inverse kinematics and FSR grasp confirmation.

  • The simulator, 14 automated tests and a GUI smoke test pass; the cross-built firmware produces ELF, HEX, BIN and MAP artifacts.
  • Implements five PWM channels, four FreeRTOS tasks, workspace checks, smooth interpolation, emergency stop, limits and retry handling.
Original Project Team Member | 2023.05 - 2023.06 | Public repository packaged 2026.07 Open GitHub Repository

Technical Skills

FPGA and Digital Logic

Verilog, Quartus, ModelSim, TimeQuest, DDS, QPSK, UART, I2C, fixed-point design and timing analysis.

Embedded Systems

C, STM32 HAL, FreeRTOS, PWM, ADC, DMA, encoders, PID, Flash, watchdogs and serial protocols.

Communications and DSP

MATLAB, modulation, constellations, BER, FFT, sampling, spectra, filtering and feature extraction.

Circuits and Engineering Tools

Altium Designer, Multisim, PCB design and soldering, Keil, and development in Windows/Linux environments.

Software and Delivery

Python, OpenCV, NumPy, Git/GitHub, Linux, Docker, SQLite/MySQL, CMake, automation scripts and technical documentation.

Project details, source and evidence are available on the site.

The resume gives a quick overview; project records preserve implementation, key code, results, limits and next steps.

Open Project Records