FPGA DDS: Blank or Corrupted Display
Symptom: DDS, PWM and statistics simulations passed, but the 74HC595 display was blank or corrupted.
Investigation: Verified the algorithm blocks separately, then checked serial bit order, segment polarity and the adc_valid update boundary.
Cause: Shift order and active display levels were inconsistent; waveform generation was not at fault.
Fix: Centralized polarity and shift order in the display module and updated statistics only on valid ADC samples.
Boundary: Simulation, compilation and timing pass; analog board I/O remains to be measured.