About Me

Test ideas through engineering.
Build capability through documentation.

I focus on communications, embedded systems, FPGA, digital signal processing and computer systems. Learning means taking a problem from principles and a working implementation through simulation, debugging and a handoff others can reproduce.

My Focus

What I Build

My current path connects communication theory, DSP, FPGA RTL, STM32/FreeRTOS, Python and engineering environments into complete practical workflows.

I care about clear inputs, outputs, boundaries and verification evidence—not merely something that appears to run. Projects retain source, tests, tool versions, constraints, result notes and known limitations wherever possible.

This site is a long-term public learning record: project pages describe implementation and evidence, articles explain methods, and lab logs preserve the debugging path.

Representative Work

Completed Practice

FPGADDS, AD/DA and board displayRTL · ModelSim · Quartus · .sof

QPSKPRBS through BER and host constellationVerilog · UART · Python

WEBLocal knowledge base and document retrievalPython · SQLite · Docker

OUTPUTEngineering records and delivery packagesDocs · Scripts · GitHub

The goal is inspectable evidence: simulation output, complete compilation, timing results, downloadable artifacts, interface contracts and end-to-end flows.

Working Style

How I Move a Project Forward

Break a large problem into independently testable stages and retain a reviewable result at each stage.

01SCOPE

Define Acceptance First

Fix the board, interfaces, use case and success criteria. FPGA acceptance includes simulation, constraints and timing; Web acceptance includes the complete user flow.

02CORE

Separate the Layers

Keep algorithm, timing, adapters and presentation separate so defects can be localized without guessing inside one large file.

03VERIFY

Debug from Evidence

Use testbenches, traces, logs, serial captures and HTTP requests. Record symptom, hypothesis, minimal experiment, cause and regression result.

04HANDOFF

Finish the Handoff

Package source, constraints, scripts, operating notes, test evidence and limitations. Planned work remains labeled as planned.

Technical Map

Current Technology

Communications and DSP: modulation, QPSK, BER, fixed-point implementation, frequency and sampling relationships.

FPGA and embedded: Verilog, ModelSim, Quartus, timing constraints, UART, I2C, AD/DA, STM32, DMA and FreeRTOS.

Software and delivery: Python, MATLAB, SQLite, Docker, Git and technical documentation for reference models, visualization, reproducibility and publication.

Boundary

How I State Limits

The site separates completed, planned and improvement work. Completed projects list toolchains and evidence; plans record architecture and acceptance criteria without presenting a blueprint as a result.

Simulation, compilation, timing closure and physical board verification are different claims. Reporting them separately makes the next missing test or measurement clear.

Start with the real projects.

The FPGA DDS, QPSK link and personal knowledge base show source, verification, handoff content and next steps.

Open Projects

Test ideas through engineering.Build capability through documentation.