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Email

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GitHub

@jiayu-here

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Topics

Areas for Discussion

FPGA

Verilog combinational, sequential and parameterized RTL design
Quartus pin assignments, compilation, resource and timing checks
ModelSim testbenches, waveform debugging and module verification
DDS phase accumulators, waveform LUTs and frequency words
QPSK Gray mapping, phase rotation, hard decisions and BER alignment

Embedded

STM32F103 clocks, GPIO, timers, ADC, UART and DMA
FreeRTOS task design, priorities, queues, mutexes and stack sizing
PWM, motor encoders, dual-wheel PID and odometry control
DS18B20, PT100, OLED, SD/FATFS and audible/visual alarms
Flash parameters, pin multiplexing, board bring-up and debugging

Communications

MATLAB signal generation, AWGN channels and multi-SNR experiments
PSK/QAM modulation, constellation mapping and symbol decisions
Time waveforms, spectra, constellations and BER curves
Normalization, feature extraction, SVM/KNN and confusion matrices
Fixed-point FFT width, scaling, quantization error and overflow

Software

Python local web tools, document parsing and retrieval workflows
SQLite/MySQL modeling, index design and SQL troubleshooting
Docker Compose, volumes, service health checks and backups
Git/GitHub branches, commits, Actions and Pages deployment
README files, automated tests, end-to-end checks and packaging