FPGA DDS: Blank or Corrupted Display
Isolates a board-display failure through shift order, active levels and valid-sample update boundaries.
Project: Multi-Function FPGA DDS Signal and Measurement System
Symptom: DDS, PWM and statistics simulations passed, but the 74HC595 display was blank or corrupted.
Hypothesis: The fault could be in DDS data, serial shift order, segment or digit polarity, or the statistics update boundary.
Investigation: Verified the algorithm blocks separately, then checked serial bit order, segment polarity and the adc_valid update boundary.
Root cause: Shift order and active display levels were inconsistent; waveform generation was not at fault.
Fix: Centralized polarity and shift order in the display module and updated statistics only on valid ADC samples.
Lesson: Isolate verified algorithm blocks before debugging board-level timing, bit order and polarity. Simulation, compilation and timing pass; analog board I/O remains to be measured.