JiaYu Here Technical Blog https://www.jiayuhere.com/en/blog/ Writing about communications, signal processing, embedded systems, FPGA and computing fundamentals. en Tue, 14 Jul 2026 00:00:00 GMT From Constellation to RTL: A Verifiable Order for Building a QPSK Link https://www.jiayuhere.com/en/blog/qpsk-from-constellation-to-rtl/ https://www.jiayuhere.com/en/blog/qpsk-from-constellation-to-rtl/ Tue, 14 Jul 2026 00:00:00 GMT A verification-first sequence for Gray mapping, phase rotation, hard decisions and BER alignment. QPSK FPGA BER Gray Non-Blocking STM32 Temperature Monitoring: From Sampling State Machines to Alarm Tasks https://www.jiayuhere.com/en/blog/stm32-temperature-nonblocking-design/ https://www.jiayuhere.com/en/blog/stm32-temperature-nonblocking-design/ Tue, 14 Jul 2026 00:00:00 GMT A dual-channel example covering non-blocking sampling, threshold management, alarm cadence, persistence and board bring-up. STM32 DS18B20 PT100 Non-blocking Alarm FPGA DDS from Frequency Word to Measurement Display: A Verifiable Path https://www.jiayuhere.com/en/blog/fpga-dds-frequency-word-to-display/ https://www.jiayuhere.com/en/blog/fpga-dds-frequency-word-to-display/ Tue, 14 Jul 2026 00:00:00 GMT Layered design and verification for the phase accumulator, waveform LUT, sample-valid contract, statistics and board display. FPGA DDS Verilog ADC Quartus MATLAB Modulation Recognition: Leakage-Free Data and Interpretable Features https://www.jiayuhere.com/en/blog/matlab-modulation-recognition-features/ https://www.jiayuhere.com/en/blog/matlab-modulation-recognition-features/ Tue, 14 Jul 2026 00:00:00 GMT A reliable workflow from signal generation and SNR injection through normalization, features and confusion-matrix analysis. MATLAB Modulation SVM Feature SNR RRT and RRT* Beyond Animation: Collision Checks, Rewiring and Repeatable Tests https://www.jiayuhere.com/en/blog/rrt-rrtstar-reliable-planner/ https://www.jiayuhere.com/en/blog/rrt-rrtstar-reliable-planner/ Tue, 14 Jul 2026 00:00:00 GMT Turn a planning animation into a testable planner through step size, edge collision, goal connection and correct RRT* rewiring. Python RRT RRT Star Collision Path Planning Five Decisions to Make Before Designing a Fixed-Point FPGA FFT https://www.jiayuhere.com/en/blog/fpga-fixed-point-fft-checklist/ https://www.jiayuhere.com/en/blog/fpga-fixed-point-fft-checklist/ Sun, 12 Jul 2026 00:00:00 GMT A design checklist covering width, scaling, twiddle factors, data order and streaming timing for fixed-point FFTs. FFT Fixed Point FPGA DSP FreeRTOS Priority Is About Urgency, Not Importance https://www.jiayuhere.com/en/blog/freertos-priority-design/ https://www.jiayuhere.com/en/blog/freertos-priority-design/ Fri, 10 Jul 2026 00:00:00 GMT Design task priorities from deadlines, blocking relationships and resource contention rather than business labels. FreeRTOS STM32 Scheduling RTOS Why MySQL Did Not Use the Index: A Structured Debugging Path https://www.jiayuhere.com/en/blog/mysql-index-debug-path/ https://www.jiayuhere.com/en/blog/mysql-index-debug-path/ Wed, 08 Jul 2026 00:00:00 GMT Diagnose missing index use through query shape, selectivity, type conversion, statistics and measured execution plans. MySQL Index SQL EXPLAIN