Communications and DSP
Move modulation, sampling, spectra, BER and fixed-point error from equations into reference models and observable data.
About
Building verifiable systems across communications, hardware and software.
I focus on communications and DSP, FPGA and embedded systems, and the software tools that support verification and delivery. This site records how a problem is defined, implemented, tested and documented—not only the final result.
Focus
Three paths I am connecting
These are not isolated labels. Together they form a complete path from signals and algorithms to hardware behavior and a reproducible handoff.
FPGA and Embedded
Use RTL, testbenches, timing constraints and board interfaces to build hardware that can be evaluated, debugged and integrated.
Software and Delivery
Use scripts, databases, containers and technical documentation for reference checks, visualization, reproducibility and publication.
Project evidence
See the direction in real projects
Each project record keeps its current verification level, key implementation details, reproduction path and unfinished work visible.
FPGACompiled and simulated
DDS Signal Generation and Measurement
Combines multi-waveform DDS, PCF8591 AD/DA, sample statistics and seven-segment display output.
View project recordCommunicationsCompiled and simulated
QPSK Digital Baseband Link
Covers PRBS, Gray mapping, a phase channel, hard decisions, BER and a host-side constellation plot.
View project recordEmbeddedSoftware loop and firmware build
Vision-Guided Robotic-Arm Sorter
Connects OpenCV detection, calibration, kinematics, a serial protocol and FreeRTOS control.
View project recordSoftwareLocally verified
Personal Knowledge Base
Uses Python, SQLite and Docker for document upload, local retrieval and optional AI answers.
View project recordEvidence boundary
State each verification level separately.
Simulation, a successful build, timing closure and physical board verification are different claims. Each page identifies the evidence that exists; hardware acceptance that has not happened remains an explicit limitation instead of being presented as a result.